A floating-point analog-to-digital architecture for a wide range-dynamic acquisition system

Abstract

In this thesis, the floating-point analog-to-digital conversion approach has been investigated for the implementation of a computer acquisition system for wide range-dynamic signals. The Floating-point A/D converters (FP-ADC) can dissociate the resolution from the wide range and thus an ADC with a moderate resolution can achieve a wide dynamic range. This dissertation studies the floating-point analog-to-digital converters and describes their characteristics and specifications. More specifically it analyses the sequential FP-ADC and improves the state of the art in conversion time as well as precision in floating-point analog-to-digital converters. It shows an implementation of the sequential FP-ADC on a daughter card which is connected to a Stratix Field Programmable Gate Array (FPGA) from Altera. The correctness of the design was verified by computer simulations while the functionality of the implemented FP-ADC on the manufactured 4-layer Printed Circuit Board (PCB) was tested on a test bench controlled by a PC.