VLSI systolic array architecture for the computation of the discrete fourier transform.

dc.contributor.author	Beraldin, Jean-Angelo.
dc.date.accessioned	2009-03-20T14:00:45Z
dc.date.available	2009-03-20T14:00:45Z
dc.date.created	1986
dc.date.issued	1986
dc.degree.level	Masters
dc.degree.name	M.A.Sc.
dc.identifier.citation	Source: Masters Abstracts International, Volume: 40-07, page: .
dc.identifier.isbn	9780315332812
dc.identifier.uri	http://hdl.handle.net/10393/5042
dc.identifier.uri	http://dx.doi.org/10.20381/ruor-10559
dc.publisher	University of Ottawa (Canada)
dc.subject.classification	Engineering, General.
dc.title	VLSI systolic array architecture for the computation of the discrete fourier transform.
dc.type	Thesis

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