Design of asynchronous sequential circuits with asynchronous unit delays.

Abstract

An asynchronous unit delay is an n-input n-output sequential circuit in which the present value of the output n-tuple is equal to the value of the input n-tuple prior to the last input change. This thesis considers the problem of realization of the asynchronous unit delay and its use in the design of asynchronous circuits. Asynchronous fundamental mode flow tables have been classified as "asynchronous definite" and "asynchronous indefinite", where asynchronous definite and asynchronous indefinite properties are modifications of the definite and indefinite properties of synchronous sequential machines respectively. It is shown that a fundamental mode table is realizable as a feedback-free connection of asynchronous unit delays if and only if the table is asynchronous definite. Straight-forward methods of realizing asynchronous definite and asynchronous indefinite flow tables without critical races by circuits of asynchronous unit delays and combinational gates are developed. The use of asynchronous unit delays avoids complicated secondary assignment problems, results in circuits with very simple structure and brings closer the theories of synchronous and asynchronous sequential machines.