Coprocessor for decoding multi-valued pseudo-random sequence patterns.

dc.contributor.advisor	Petriu, Emil,
dc.contributor.author	Moica, Adrian.
dc.date.accessioned	2009-03-23T18:26:38Z
dc.date.available	2009-03-23T18:26:38Z
dc.date.created	2000
dc.date.issued	2000
dc.degree.level	Masters
dc.degree.name	M.A.Sc.
dc.description.abstract	This thesis discusses generalized Pseudo-Random Multi-Valued Sequence (PRMVS) encoding and corresponding PRMVS-to-natural code conversion algorithms. A hardware architecture implementing in real-time this generalized code conversion algorithm is implemented as a programmable Pseudo-Random DECoder (PRDEC) coprocessor. This coprocessor is intended to work in microprocessor-based embedded systems where it is seen as an 8-bit memory mapped device by the system microprocessor. The coprocessor architecture is implemented and simulated using VHDL.
dc.format.extent	192 p.
dc.identifier.citation	Source: Masters Abstracts International, Volume: 39-04, page: 1218.
dc.identifier.isbn	9780612571457
dc.identifier.uri	http://hdl.handle.net/10393/9262
dc.identifier.uri	http://dx.doi.org/10.20381/ruor-16226
dc.publisher	University of Ottawa (Canada)
dc.subject.classification	Engineering, Electronics and Electrical.
dc.title	Coprocessor for decoding multi-valued pseudo-random sequence patterns.
dc.type	Thesis

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