Coprocessor for decoding multi-valued pseudo-random sequence patterns.

Abstract

This thesis discusses generalized Pseudo-Random Multi-Valued Sequence (PRMVS) encoding and corresponding PRMVS-to-natural code conversion algorithms. A hardware architecture implementing in real-time this generalized code conversion algorithm is implemented as a programmable Pseudo-Random DECoder (PRDEC) coprocessor. This coprocessor is intended to work in microprocessor-based embedded systems where it is seen as an 8-bit memory mapped device by the system microprocessor. The coprocessor architecture is implemented and simulated using VHDL.