Static task scheduling for configurable multiprocessors

dc.contributor.author	Groza, Voicu
dc.contributor.author	Bolic, Miodrag
dc.contributor.author	Montcalm, Michael
dc.contributor.author	Shapiro, Daniel
dc.date.accessioned	2010-05-04T16:01:25Z
dc.date.available	2010-05-04T16:01:25Z
dc.date.created	2010
dc.date.issued	2010-05-04T16:01:25Z
dc.description.abstract	Our task scheduling pass implemented in the COINS compiler uses a Binary Linear Programming model for scheduling a program into a multiprocessor system-on-chip where each processor can be accelerated with instruction set extensions. We compare our work to state of the art approaches and estimate an average speedup of 4.01 in application execution time compared to a sequential approach. We estimate on average a 1.43 times speedup over the use of multiprocessor scheduling without instruction set extensions.
dc.description.sponsorship	NSERC
dc.identifier.uri	http://hdl.handle.net/10393/12896
dc.language.iso	en
dc.subject	Instruction set extension
dc.subject	Application specific instruction-set processor
dc.subject	Multiprocessor static scheduling
dc.title	Static task scheduling for configurable multiprocessors
dc.type	Working Paper

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