Studies on a continuous Markov model for probabilistic fault analysis in VLSI sequential circuits using computer simulation.

Abstract

A continuous parameter Markov model is proposed in this thesis to detect permanent stuck-at faults in sequential circuits by random testing. Given a sequential circuits with certain stuck-at faults specified, the fault-free and the faulty state tables of the circuit can be readily derived. By simulation of these two state tables on a computer, the parameters of the desired Markov model can be obtained. For a specified confidence level, it is easy to derive the model parameters and to estimate the required testing time. A complete mathematical analysis of the model is given that provides some useful insights into the nature of faults in relation to random testing and the associated confidence level.