Modeling and analysis of packet switch architectures for broadband ISDN.

Abstract

In this thesis we analyze broadband switching architectures based on the Asynchronous Transfer Mode (ATM). Many architectures have been proposed in the literature for high-speed packet switches. We first review some of these switch architectures and their performance. The high-performance switch architectures, in general, require that the buffers be placed at the output ports. These output buffered switches tend to have large hardware complexity or require high speedup in their operation. Our focus is on high-performance switch architectures with low speedup output buffers or a shared buffer. An N $\times$ d ATM switch with finite output buffers is modeled as a discrete-time queue. The case d = 1 represents an ATM multiplexer with N input source and a finite capacity buffer. Loading at the input as well as at the output is considered to be imbalanced, which greatly affects the switch performance especially the hot spot traffic pattern. We also consider the switch with reduced speedup. In this case, the number of cells going to an output buffer in one time slot is limited to L N. This greatly simplifies the implementation of the switch. The arrivals to an input port of the switch, besides being bursty, are correlated in the sense that a burst arriving to an output port brings with it several cells belonging to the same virtual connection. As a worst case, we assume that consecutive cells in a burst are heading to the same output port. This greatly affects the dimensioning of the switch buffer. The input process to each input port is modeled by an Interrupted Bernoulli Process (IBP). We have developed an aggregation technique which allows the reduction of the state space that describes the arrival processes to the switch. This makes handling the output buffer driven by the induced process more manageable. Traffic priorities in ATM networks is an important issue because such networks will support applications with diverse traffic characteristics. In the light of this, we consider traffic priorities in an output buffered switch and in a completely shared-buffer switch. The transient analysis of the output buffer is also studied by considering the mean time until buffer overflow. The switch architecture that has the maximum mean-time-to-blocking is favorable. The busy period of the output buffer is also characterized. In routing the whole burst to an output buffer, the output process becomes more bursty than the input process.