Tunable Instruction Set Extension Identification

Abstract

In this work a tunable algorithm for instruction set extension identification is presented. The goal is to find a set of extensions to the instruction set which reduces application execution time. This novel approach enables the user to trade application speedup for compiler execution time. This approach shows benefit only when a binding hardware area constraint is applied to the design space. Several experiments are presented. An average improvement in application speedup of 4.5% over the state of the art approach was observed, and some instances of our approach were as much as 25.8% better than the state of the art. The aforementioned results are merely samples in a large design space, and we conclude that our novel algorithm can provide valuable advantages over state of the art approaches.