Design of Multi-junction Solar Cells on Silicon Substrates Using a Porous Silicon Compliant Membrane

Abstract

A novel approach to the design of multi-junction solar cells on silicon substrates for 1-sun applications is described. Models for device simulation including porous silicon layers are presented. A silicon bottom subcell is formed by diffusion of dopants into a silicon wafer. The top of the wafer is porosified to create a compliant layer, and a III-V buffer layer is then grown epitaxially, followed by middle and top subcells. Due to the resistivity of the porous material, these designs are best suited to high efficiency 1-sun applications. Numerical simulations of a multi-junction solar cell incorporating a porous silicon compliant membrane indicate an efficiency of 30.7% under AM1.5G, 1-sun for low threading dislocation densities (TDD), decreasing to 23.7% for a TDD of 10^7 cm^-2.