Design and implementation of instruction set extension identification for a multiprocessor system-on-chip hardwaresoftware co-design toolchain

Abstract

Designers of embedded systems are faced with the challenge of creating systems containing customized processors. Efficient algorithms for the automated identification of extensions to processor instruction sets are needed, as well as flexible tools for the specification and generation of customized embedded systems. This work on instruction set extension identification is part of a larger effort to design a multiprocessor system design tool. An algorithm for the identification of instruction set extensions is presented along with four approaches for improving the state of the art. In this research we addressed two important aspects of instruction set extension identification: reducing compiler execution time and identifying more instructions. Using the approaches described here, we achieved a compiler execution time speedup over the baseline compiler configuration as high as 3.8 times, and showed that compared to another popular approach our method identifies between 9.5 and 20 times the number of instruction set extensions.