Approach to coverage-driven functional verification of complex multimillion gate ASICs

Abstract

Today ASICs' designs are very complex and each consists of multi-millions gates. This creates a difficult and almost an impossible task for the verification engineers to verify thoroughly the whole design. The complexity of the verification effort grows exponentially. The most common verification methodology used today is Deterministic Testing. Based on today large designs, hundreds of deterministic test cases are required to verify the whole design. This is very time consuming and it requires lots of engineers' manpower. Since time to market is very essential, the engineers are forced to send the ASIC for fabrication even though lots of functionalities are not covered. A solution to this problem is Coverage-Driven Functional Verification (CDV). The CDV approach is based on ASICs functionalities. The verification process is done in the early stages of the design. In fact it is done right after the ASICs specifications are outlined and in parallel with RTL development. Functional Coverage is performed by collecting coverage items that correspond to ASICs functionalities. Using Functional coverage would minimize the number of test cases and enhance the verification process. In this thesis, the "Ethernet IP Core" Verilog design from OpenCores will be used. The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of the Ethernet standard. Both the Deterministic Testing Approach and the Coverage-Driven Functional Verification will be applied on the Ethernet IP Core design. Both verification methodologies will be compared and a conclusion will be driven to prove that CDV is the way for verifying today complex multi-millions gates ASICs. Cadence Specman (e language - IEEE 1647 e) is chosen as the verification tool because it provides different features for the Coverage-Driven Functional Verification Methodology.