VHDL design and implementation of high speed blind equalizer

Abstract

Blind equalization has significant advantages over conventional adaptive equalization because of its self-recovery ability. This ability makes blind equalization the best choice in broadcasting type communication. With increased demands for broadband data communication, the speed of blind equalization is continuously increasing. The main challenge lies in designing a high speed blind equalizer using current VLSI technology. Different blind equalization algorithms were investigated for this thesis. Comparisons of their performances and hardware complexities were performed. The CM algorithm offers excellent performance and the most robust property. A pipelined transposed direct form structure equalizer based on the CM blind equalization algorithm was proposed and designed in a VHDL model. Its performance was verified and the finite wordlength effect was investigated. VHDL model was synthesized using 0.25 mum technology.