VHDL design and implementation of a LAN on a chip.

Abstract

With ever increasing usage of Internet and more demand for real-time applications, the intrinsic shortcoming of Ethernet becomes more and more apparent. Ethernet architecture combined with the Medium Access Control protocol can not guarantee a maximum time delay variation, jitter, which is critical to real-time applications. In this thesis, a novel LAN architecture is proposed, designed and implemented with field programmable gate array (FPGA) device as target. This LAN on a chip design is simple, scaleable and modular. The preliminary simulation shows that it reduces the impact of packet collision on the LAN and improves the performance in terms of reducing and limiting jitter on real-time traffic.