SCFL VLSI circuits for improved yield.

Abstract

In this thesis an improvement to the Gallium Arsenide source coupled FET logic ECL output cell is presented. Because of parameter variations from site-to-site in the wafer, ECL compatibility of source coupled FET logic circuits, in terms of voltage levels and clock duty cycle, was very poor and therefore the electrical yield was very low. A source coupled FET logic buffer driver was designed to make the Gallium Arsenide ECL cell more resistant to parameter variations and consequently, the yield is highly improved. Furthermore, multi-site circuits are now possible with a high output electrical yield. The circuit complexity is limited by the latency problem which occurs when using both high and low frequency signals to drive the gate. In this research, the latency time period is reduced by over 75% and hence either the operating frequency or the complexity can be increased six times.