Discrete wavelet transform architecture for image coding and decoding

dc.contributor.advisor	Petriu, E.,
dc.contributor.author	Huluta, Emanuil
dc.date.accessioned	2013-11-07T17:24:39Z
dc.date.available	2013-11-07T17:24:39Z
dc.date.created	2003
dc.date.issued	2003
dc.degree.level	Masters
dc.degree.name	M.A.Sc.
dc.description.abstract	This thesis analyses and implements a Discrete Wavelet Transform (DWT) architecture for image processing. The architecture comprises two modules, one for image coding and the other for image decoding. Each module is implemented using a novel Modified Forward-Backward Register Allocation (MFBRA) method and accommodates two Fast Processing Elements (FPE). The resulting architecture minimizes the hardware required to perform the task together with reduced processing time, rendering the whole structure suitable for real time applications. The whole architecture is implemented and simulated using the Verilog Hardware Description Language.
dc.format.extent	97 p.
dc.identifier.citation	Source: Masters Abstracts International, Volume: 42-06, page: 2290.
dc.identifier.uri	http://hdl.handle.net/10393/26491
dc.identifier.uri	http://dx.doi.org/10.20381/ruor-9655
dc.language.iso	en
dc.publisher	University of Ottawa (Canada)
dc.subject.classification	Engineering, Electronics and Electrical.
dc.title	Discrete wavelet transform architecture for image coding and decoding
dc.type	Thesis

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