Yield study of gallium arsenide VLSI circuits.

Abstract

In this thesis a comparison of two gallium arsenide digital logic families, direct-coupled FET logic (DCFL), and source-coupled FET logic (SCFL) is presented. Then, a study of the electrical yield characteristics of gallium arsenide SCFL circuits is done according to the following parameters: The maximum frequency of operation, the compatibility with ECL in terms of logic levels, the circuit architecture, and the complexity. This study is carried out taking into account the presence of parametric variations as obtained from measurements from a typical wafer. The compatibility with ECL is found to be the determinant factor on the maximum achievable yield. The circuit architecture and complexity, on the other hand, are found to have a significant effect on the maximum circuit speed that can be achieved for the maximum yield.