Soft Co-Processor Based Hardware Acceleration for Image Blending
| dc.contributor.author | Shapiro, Daniel | |
| dc.contributor.author | Parri, Jonathan | |
| dc.contributor.author | Desmarais, John-Marc | |
| dc.contributor.author | Kouri, Abdullah | |
| dc.contributor.author | Bergeron, Jean-Philippe | |
| dc.contributor.author | Bolic, Miodrag | |
| dc.date.accessioned | 2011-03-14T14:14:09Z | |
| dc.date.available | 2011-03-14T14:14:09Z | |
| dc.date.created | 2011 | |
| dc.date.issued | 2011-03-14 | |
| dc.description.abstract | The speed of software algorithms can be greatly improved by using a co-processor to offload computations from the main processor. Multiple co-processors can further increase the speed of a given algorithm. Based on this idea, three versions of an alpha blending algorithm were implemented on a NIOS II/f. The first implementation was entirely software based. This software based solution was then used as a baseline against which to test a single co-processor hardware solution and a multiple co-processor hardware solution. We showed that a single co-processor implementation achieved a speedup of 13.2 times, whereas the 2 co-processor solution achieved a speedup of 14.5 times with respect to this baseline. As further co-processors were added, the system became memory-bound as the algorithmic bottleneck moved from processing power to memory throughput. | |
| dc.description.sponsorship | NSERC | |
| dc.identifier.uri | http://hdl.handle.net/10393/19832 | |
| dc.identifier.uri | http://www.site.uottawa.ca/~dshap092/ | |
| dc.language.iso | en | |
| dc.subject | alpha blending | |
| dc.subject | Instruction set extension | |
| dc.subject | image processing | |
| dc.subject | FPGA | |
| dc.title | Soft Co-Processor Based Hardware Acceleration for Image Blending | |
| dc.type | Working Paper |
