Performance evaluation of FASTRAC ABR control algorithm with VSVD under long propagation delay.

Abstract

There have been many control algorithms proposed in the literature for handling the flow control of the Available Bit Rate (ABR) class of service on ATM. But few have demonstrated sound theoretical development, compliance to TM4.0, and a practical design. This thesis attempts to formalize and present ABR flow control from fundamentals to illustrate the requirements for designing a better algorithm. It explains TM4.0 ABR control rules and highlights subtleties in the standards that are commonly missed in the literature; these factors result in non-compliance and render the proposed algorithms impractical. This thesis also attempts to present various practical switch designs and their capabilities for ABR support. It applies traditional control theory to ABR flow control. It demonstrates that understanding the combination of all these three aspects is key to designing ABR control algorithms that are theoretically sound and practical. A rate thresholding explicit rate (ER) based control algorithm, FASTRAC (FAST RAte Computation), is the focus of the simulation analysis. (Abstract shortened by UMI.)