Improved test efficiency in IP cores using ModelSim verification tool

Abstract

The complexity of modern digital circuit has increased enormously particularly in the context of paradigm shift from system-on-board to designs embracing embedded cores-based System-on-Chips (SoCs). This increased complexity of circuits in turn results in a huge challenge of setting up their appropriate fault testing environments. Though lots of efforts have been taken to rapidly test the very large scale integrated (VLSI) circuit chips with very reasonable cost, with advances in technology, new frontiers also emerged. This thesis aims at developing a new technique to verify and test architecture of circuits under hardware and software co-design environment, targeting specifically embedded cores-based systems-on-chip. The well-known concept, design for testability (DFT), is utilized in this thesis based on the use of ModelSim simulation and verification tool to simulate the entire design. Some partial results on ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits are provided along with a comparison of the results from some earlier works.