VLSI architecture for Discrete Wavelet Transform.

dc.contributor.advisor	Yeap, T.,
dc.contributor.author	Grzeszczak, Aleksander.
dc.date.accessioned	2009-03-25T19:59:43Z
dc.date.available	2009-03-25T19:59:43Z
dc.date.created	1995
dc.date.issued	1995
dc.degree.level	Masters
dc.degree.name	M.A.Sc.
dc.description.abstract	In this thesis, we present a new simple and efficient VLSI architecture (DWT-SA) for computing the Discrete Wavelet Transform. The proposed architecture is systolic in nature, modular and extendible to 1-D or 2-D DWT transform of any size. The DWT-SA has been designed, simulated and implemented in silicon. The following are the features of the DWT-SA architecture: (1) It has an efficient (close to 100%) hardware utilization. (2) It works with data streams of arbitrary size. (3) The design is cascadable, for computation of one, two or three dimensional DWT. (4) It requires a minimum interface circuitry on the chip for purposes of interconnecting to a standard communication bus. The DWT-SA design has been implemented using CMOS 1.2 um technology.
dc.format.extent	136 p.
dc.identifier.citation	Source: Masters Abstracts International, Volume: 34-04, page: 1648.
dc.identifier.isbn	9780612049246
dc.identifier.uri	http://hdl.handle.net/10393/9908
dc.identifier.uri	http://dx.doi.org/10.20381/ruor-8029
dc.publisher	University of Ottawa (Canada)
dc.subject.classification	Engineering, Electronics and Electrical.
dc.title	VLSI architecture for Discrete Wavelet Transform.
dc.type	Thesis

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