Hardware linked-list using FPGAs and optical central stage impairments in a sectored packet switch with an optical core (demonstrator)

Abstract

Packet switches play a key role in packet-switched networks and are at the very core of the design in routers. The recent decade has enabled photonics to produce high-speed reliable networks; however within these networks the switching aspect remains mostly within the electrical domain. Opto-electrical and Electro-optical conversion is required for packet headers to be identified in order to forward the packets to their appropriate destination link. Convergence to a more optical solution depends on specific packet-switch architectures. This thesis presents on two aspects of building a "hardware demonstrator" of a CLOS-like optoelectronic packet switch architecture that consists of two stages of electronic islands (called "sectors") surrounding a photonic central stage. The hardware demonstrator is a scaled-down version of the switch and is intended to "demonstrate" the concepts and workings of the architecture. The first aspect is a detailed description and simulation of a System-on-Chip (SoC) linked-list memory manager implemented in a Field-Programmable Gate Array (FPGA) that is a building block of a common shared-memory switch that forms an electronic sector. If the core optical central stage is very far from the input and output sectors or if the switch is scaled to higher port counts, then key optical impairments need to be identified. The second part of this thesis explores the impairments for a wavelength selectable switch used in a cross-connect configuration as a possible switching technology and shows optical measurements for each of the identified impairments.