A system-on-a chip testing methodology

Abstract

In this thesis, we present a system-on-a chip testing methodology. The system consists of a wrapper, test access mechanism and the cores under test. The cores include the ISCAS sequential and combinational benchmark circuits. At the gate level, stuck at fault model is used to detect faults. The wrapper separates the circuit under test from other cores. The test access mechanism transports the test patterns or test vectors to the desired circuit under test and then transports the responses back to the output pin of the SOC. The faults are then injected using the fault simulator that generates test for the circuit under test. Out of the many TAM design methods, we implemented the TAM as a plain signal transport medium, which is shared by all the cores in the system-on-chip. Once the dedicated TAM lines are set to the circuit under test, fault simulation is done. Each circuit in an SOC is independently tested for its fault coverage. The isolation of the circuit under test from the others is taken care by the program running in the background. We were able to simulate the whole SOC testing and get satisfactory fault coverage for the circuits under tests.