Generalized mergeability in space compression using nonexhaustive test patterns for built-in self-testing of VLSI circuits: Mathematical analysis and simulation results.

Abstract

This thesis deals with response compaction techniques of BIST of VLSI circuits which translates into a process of reducing the test response of the circuit under test (CUT) to a signature. Instead of comparing bit by bit the fault free responses to the observed outputs of the CUT as in conventional testing, here the observed signature is compared to the correct one, thereby reducing the storage requirements for the correct CUT responses. The thesis specifically deals with designing efficient space compaction techniques for BIST of VLSI circuits using nonexhaustive test sets. The developed techniques utilize the concepts of Hamming distance, sequence weights (generalized), and failure probabilities with multiplicities of errors at the CUT output in selecting specific gates for merger of a number of outputs streams from the CUT using a generalized mergeability criteria. The criteria are developed under conditions of both stochastic independence and stochastic dependence of line errors. Design algorithms are proposed in the thesis and the methods of implementation were demonstrated with many examples. (Abstract shortened by UMI.)