Neural network digital hardware implementation

dc.contributor.authorPasca, Isabela Mona
dc.date.accessioned2013-11-07T19:02:54Z
dc.date.available2013-11-07T19:02:54Z
dc.date.created2007
dc.date.issued2007
dc.degree.levelMasters
dc.degree.nameM.A.Sc.
dc.description.abstractThis thesis presents a digital hardware implementation of an artificial neuron with learning ability using the QuartusII 5.1sp1 web edition software on Altera's University Program Development Board (UP2). The learning method implemented is neither backpropagation nor conjugate gradient, but the weight simultaneous perturbation. By combining this method with a pulse density system and using a Field Programmable Gate Array, an interesting artificial neuron hardware architecture is obtained. Finally, two applications of the neuron implementation are presented: an analog function and a digital function.
dc.format.extent141 p.
dc.identifier.citationSource: Masters Abstracts International, Volume: 47-06, page: 3714.
dc.identifier.urihttp://hdl.handle.net/10393/27902
dc.identifier.urihttp://dx.doi.org/10.20381/ruor-18972
dc.language.isoen
dc.publisherUniversity of Ottawa (Canada)
dc.subject.classificationEngineering, Electronics and Electrical.
dc.titleNeural network digital hardware implementation
dc.typeThesis

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