Stochastic modeling in fault testing of decomposable sequential circuits through computer simulation.

Abstract

The increasing complexity of today's digital devices has rendered the problem of fault detection, fault analysis, and test generation extremely difficult. Test generation for sequential circuits has been a difficult task. This is due to the large search space to be considered in test pattern generation. Different approaches have been taken in the past to solve the problem of fault detection and test generation in sequential circuits. A popular approach, called the scan design, is often used where the test generation problem in sequential circuits is transformed into one of combinational circuits. Unfortunately, this approach is mostly restricted to synchronous sequential circuits free of critical races. Moreover, when a circuit is very large and complex, the test generation can be quite involved, making the ad hoc approaches ineffective. Therefore, alternative methods should be considered. In this thesis, the detection of permanent faults in sequential circuits by random testing is analyzed utilizing the circuit partitioning approach together with a continuous parameter Markov model. Given a large decomposable sequential circuit, it is partitioned into several smaller partitions using either serial or parallel decomposition. For each partition with certain stuck faults specified, the original state table and its error version are derived from an analysis of the partition under fault-free and faulty conditions, respectively. Then by simulation of these two tables on a computer, the parameters of the desired Markov model are obtained. For a specified degree of confidence, it is easy to derive the parameters of the Markov model and to calculate the required lengths of random test patterns.