Telecommunications call processing on a linear processor array.

Abstract

New telephone features and their increasingly complex interactions with one another requires better performance from Telecommunication Switching systems. Since call processing is the most computationally expensive task in a switch, multi-processor systems are being considered for the call processing cores of many commercial switch architectures. In this thesis, the design criteria for such a call processing system have been generated and analyzed. A new approach, the heterogeneous linear pipelined array is proposed and compared with a common load sharing architecture. The linear pipelined array has been simulated using a detailed Verilog Hardware Description Language model, to further verify its suitability for call processing applications. Several fixed assignment schemes and three simple heuristic assignment schemes have been simulated and the resulting throughput and processor utilizations has been studied. A semi-static approach has been tested, where an optimal schedule is determined based on the relative quantities of calls in specific states. The performance of the array for the call processing task is shown, for a variety of cases, to be dependent on the degree of load balancing which can be achieved in the array and the extent to which processing bottlenecks can be avoided. The results for the semi-static schedules are significantly better than for the fixed schemes. (Abstract shortened by UMI.)