Response data compaction in BIST under generalized mergeability based on switching theory formulation and utilizing a new measure of failure probability.

Abstract

The present thesis deals with the general problem of designing and analyzing efficient space compression techniques for built-in self-testing of VLSI circuits using compact test sets. The techniques are based on identifying certain inherent properties of the test data responses of the CUT along with the knowledge of nonoccurrence of failure probabilities. To that effect, generalized mergeability criteria are developed in the thesis that utilize the well known switching theory concepts of Hamming distance, cover table, and frequency ordering of literals in conjunction with those of sequence weights (first-order and Nth-order) and derived sequences. The thesis also explores the effect on sequence mergeability under constraints of stochastic independence of multiple line errors and its outcome on the fault coverage. Extensive simulation experiments on ISCAS 85 combinational benchmark circuits with FSIM, ATALANTA, and COMPACTEST programs indicate that the proposed techniques achieve a relatively high fault coverage for single stuck-line faults with low CPU simulation time and acceptable area overhead for the designed compactors. The subject thesis also rates the performance of the designed compactors with that of the conventional linear parity tree space compactors. (Abstract shortened by UMI.)