Computational*RAM implementations of vector quantization for image and video compression.

Abstract

In this thesis, Computational$\sp*$RAM (C$\sp*$RAM) implementations of Vector Quantization for image and video compression is proposed. Vector Quantization (VQ) is a powerful technique for low bit rate image and video compression. The coding performance can be further improved by employing the adaptive techniques at the expense of significant increase in computational complexity. Recently, a number of VLSI architectures for implementing VQ have been reported in the literature. These architectures are not programmable and rather complex. We proposed the mapping of VQ-based image and video compression algorithms on the C$\sp*$RAM architecture. C$\sp*$RAM is a SIMD-memory hybrid where the processing elements are attached to memory columns of a conventional RAM to take advantage of the on-chip high memory bandwidth for parallel computation. Implementation of VQ based on the mean absolute error measure using the C$\sp*$RAM's parallel structure is first presented. This follows with the details of the proposed Modified Scalable VQ algorithm. C$\sp*$RAM implementation of Modified SVQ is a mapping of binary tree onto parallel structure which results in scalable bit stream. We then propose a novel adaptive codebook replenishment VQ and index-based motion estimation (AVQ + ME) algorithm for video compression. Finally, the C$\sp*$RAM implementation of AVQ + ME is presented. Simulation results demonstrate a good coding performance at a significantly reduced computational complexity.