Fractal engine: An affine video processor core for multimedia applications.

Abstract

The recent advances in VLSI technology, high-speed processor designs, Internet/Intranet implementations, broadband networks (ATM and ISDN) and compression standards are leading to the popularity of multimedia applications. In general, multimedia computing presents challenges from the perspectives of both hardware and software. Each medium in a multimedia environment requires different processes, techniques, algorithms and hardware. Hence, it is crucial to design a generic processor architecture that meets the computing requirements of the various media types. In another word, there is a need for a bottom-up design strategy for meeting the computing needs of multimedia processing. In this thesis, we propose the design of an affine video processor termed Fractal Engine. We have first derived the fundamental operations involved in visual processing tasks and designed the generic processing elements to map a majority of these operations. We have chosen affine transformations as the target algorithm as it is expected to be increasingly used in many visual-processing applications including latest video coding standard MPEG4. We have chosen fractal block processing (FBP) as a candidate algorithm for the design of target video processor, since it encompasses a variety of visual processing operations including affine transforms. Fractal Engine is capable of implementing the gamut of image/video processing algorithms. Fractal Engine is a simple, modular, and scalable architecture that is optimized to execute both low-level and mid-level operations. It is capable of implementing a variety of visual processing tasks. Fractal Engine is an open architecture and is therefore capable of adapting to the processing requirements of a variety of media processing algorithms. The individual modules of the Fractal Engine have been implemented in VHDL. A behavioral model of the circuit has been developed and fully tested by using VHDL simulators. The model is synthesized using BiCMOS .8mu ASIC library cells and Xilinx/Altera FPGAs. We have chosen to demonstrate the real-time execution capability of Fractal Engine by mapping specific visual processing algorithms such as fractal block coding (FBC), vector quantization and motion estimation onto the proposed architecture.