Space compactor design in BIST with maximal compaction ratio using concepts of strong and weak compatibilities of response data

Abstract

Built-in self-testing (BIST) is a design process that provides the capability of solving many of the problems otherwise encountered in testing today's complex system on a chip circuits. With the increasing number of I/O counts in system on a Chip circuits it is almost impossible to think of BIST with out a space compactor. The fundamental problem with space compactors is error masking or aliasing, which occurs when the signatures from faulty output responses map into fault free signatures resulting reduced test quality. This theses develops a new approach for implementing space-efficient BIST support hardware, extending the well known concepts of conventional switching theory, and of compatibility relation as employed in the minimization of incomplete sequential machines, using Paull-Unger algorithm of finding all the maximal compatibility classes in the design. The theses utilizes mathematical selection criteria of merger of an optimal number of output lines of the MUT to decide on the logic for zero-aliasing, achieving maximal compaction in the design, as is evident from the simulation experiments conducted on ISCAS 85 and ISCAS 89 benchmark circuits.