Syndrome signature in built-in self-testing of VLSI circuits.

Abstract

Testing has become very important in the context of modern VLSI and is a severe challenge for testing engineers. A number of basic analytic and heuristic methods exists for the solution of the fault detection and location problem in combinational circuits. Classical testing of combinational circuits requires a list of fault-free responses of the circuit to the test set. For most practical circuits implemented today, the large storage requirement makes the test procedure very expensive. In this thesis, a syndrome signature is proposed that is particularly well suited for exhaustive testing of VLSI circuits and is based on the idea originally developed by Savir for syndrome testing. A syndrome is defined as the number of minterms realized by a function under exhaustive application of all possible input patterns. Given an n-input combinational circuit, a syndrome signature is defined by an (n + 1)-element vector consisting of the primary syndrome of the circuit function F and n other subsyndromes corresponding to the subfunctions obtained by setting the ith variable in F equal to 0 or 1. A multiple-output syndrome signature generation is also discussed, which preserves the desirable properties of the conventional single-output circuits response analyzers. The proposed technique was simulated on various combinational circuits and the results look very promising. The signature generators can be easily implemented using the current VLSI technology.