Space compactor design for built-in self-testing of VLSI circuits from compact test sets using sequence characterization and failure probabilities.

Abstract

A new space compaction technique for built-in self-testing (BIST) of VLSI circuits using compact test sets with the primary objective of minimizing the storage required for the circuit under test (CUT) while maintaining fault coverage information is presented in this dissertation. The compaction technique utilizes the concepts of the Hamming distance and sequence weight, together with the use of failure probabilities of the errors in the selection of specific gates for merger of a pair of output streams from the CUT. The outputs coming out of the space compactor may eventually be fed into a time compactor (syndrome counter) to derive the signature for the circuit. The proposed technique guarantees a simple design with a very high fault coverage for simple stuck-line faults, with low CPU simulation time, and acceptable area overhead. Design algorithms are proposed and the simplicity and ease of implementation are demonstrated with numerous examples. Specifically, extensive simulation runs on ISCAS 85 combinational circuits with FSIM, ATALANTA, and COMPACTEST confirm the efficiency of the suggested approach under conditions of stochastic independence as well as dependence of single line and double line output errors. A performance comparison of the designed space compactor with a conventional linear parity tree compactor is also presented.