Fares, George E.2009-03-202009-03-2019891989Source: Masters Abstracts International, Volume: 40-07, page: .9780315563926http://hdl.handle.net/10393/5937http://dx.doi.org/10.20381/ruor-14609Engineering, General.Probabilistic fault location in combinational logic networks by multistage binary tree classifier algorith development, implementation results and efficiency.Thesis