VLSI systolic array architecture for the computation of the discrete fourier transform.

Beraldin, Jean-Angelo.2009-03-202009-03-2019861986Source: Masters Abstracts International, Volume: 40-07, page: .9780315332812http://hdl.handle.net/10393/5042http://dx.doi.org/10.20381/ruor-10559Engineering, General.VLSI systolic array architecture for the computation of the discrete fourier transform.Thesis