Petriu, Emil,Moica, Adrian.2009-03-232009-03-2320002000Source: Masters Abstracts International, Volume: 39-04, page: 1218.9780612571457http://hdl.handle.net/10393/9262http://dx.doi.org/10.20381/ruor-16226This thesis discusses generalized Pseudo-Random Multi-Valued Sequence (PRMVS) encoding and corresponding PRMVS-to-natural code conversion algorithms. A hardware architecture implementing in real-time this generalized code conversion algorithm is implemented as a programmable Pseudo-Random DECoder (PRDEC) coprocessor. This coprocessor is intended to work in microprocessor-based embedded systems where it is seen as an 8-bit memory mapped device by the system microprocessor. The coprocessor architecture is implemented and simulated using VHDL.192 p.Engineering, Electronics and Electrical.Thesis