Yeap, T.,Grzeszczak, Aleksander.2009-03-252009-03-2519951995Source: Masters Abstracts International, Volume: 34-04, page: 1648.9780612049246http://hdl.handle.net/10393/9908http://dx.doi.org/10.20381/ruor-8029In this thesis, we present a new simple and efficient VLSI architecture (DWT-SA) for computing the Discrete Wavelet Transform. The proposed architecture is systolic in nature, modular and extendible to 1-D or 2-D DWT transform of any size. The DWT-SA has been designed, simulated and implemented in silicon. The following are the features of the DWT-SA architecture: (1) It has an efficient (close to 100%) hardware utilization. (2) It works with data streams of arbitrary size. (3) The design is cascadable, for computation of one, two or three dimensional DWT. (4) It requires a minimum interface circuitry on the chip for purposes of interconnecting to a standard communication bus. The DWT-SA design has been implemented using CMOS 1.2 um technology.136 p.Engineering, Electronics and Electrical.Thesis