Digital core output test data compression architecture based on switching theory concepts: Model implementation and analysis - Assaf, Mansour Hanna (University of Ottawa (Canada), 2003)
The design of space-efficient support hardware for built-in self-testing (BIST) is of critical importance in the design and manufacture of VLSI circuits. This dissertation reports new space compression techniques for particular use in digital core based systems which facilitate designing compression networks using compact or pseudorandom test sets, with the target objective of minimizing the storage requirements for the module under test (MUT), while maintaining the fault coverage information. The suggested techniques take advantage of some well known concepts of conventional switching theory, particularly those of cover table and frequency ordering as commonly utilized in the minimization of switching functions, besides knowledge of Hamming distance, sequence weights, and derived sequences in the selection of specific gates for merger of an arbitrary number of output bit streams from the MUT. The outputs coming out of the space compactor may eventually be fed into a time compressor ( viz. syndrome counter) to derive the MUT signatures. The approaches developed to designing zero-aliasing space compressors utilizing additionally concepts of strong and weak compatibilities of response data outputs are novel in the sense that zero-aliasing is achieved without modification of the MUT, while maximal compaction is achieved in most cases in reasonable time utilizing some simple heuristics. The techniques proposed in the dissertation guarantee simple design with a high or full fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead. Design algorithms are proposed in the dissertation, and the simplicity and ease of their implementations are demonstrated with numerous examples. Specifically, extensive simulation nuns on ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits with FSIM, ATALANTA, HOPE, and COMPACTEST programs confirm the usefulness of the suggested approaches under conditions of both stochastic independence and dependence of single and multiple fine errors. A performance comparison of the designed space compressors with conventional linear parity tree space compactors as benchmark is also presented in the dissertation, where zero-aliasing is not realized, which demonstrates improved tradeoff for the new circuits between fault coverage and the MUT resources consumed contrasted with existing designs, thereby aiding to fully appreciate the enhancements. However, for the zero-aliasing compactors, advantages are clearly obvious.
Keywords: Engineering, Electronics and Electrical.