VHDL implementation of turbo codec

FieldValue
dc.contributor.advisorYeap, Tet,
dc.contributor.advisorChouinard, Jean-Yves,
dc.contributor.authorTong, Yanhui
dc.date.accessioned2013-11-07T17:24:14Z
dc.date.available2013-11-07T17:24:14Z
dc.date.created2003
dc.date.issued2003
dc.identifier.citationSource: Masters Abstracts International, Volume: 41-06, page: 1804.
dc.identifier.urihttp://hdl.handle.net/10393/26405
dc.identifier.urihttp://dx.doi.org/10.20381/ruor-18171
dc.description.abstractTurbo coding is one of the most significant achievements in coding theory during the last decade. It has been shown in the literature that transmission systems employing turbo codes could achieve a performance close to the Shannon limit. Turbo decoding is the major contributor to the overall complexity of turbo coding. Therefore, the challenge is to implement turbo coding in various communications systems at affordable decoding complexity using current VLSI technology. Four different turbo decoding algorithms were investigated in this thesis. Comparisons on both their performances and implementation complexities were performed. Log-MAP based turbo decoding offers the best compromise among the different turbo decoding algorithms. A Register-Transfer-Level (RTL) fixed-point turbo decoder model based on Log-MAP algorithm was designed and simulated using VHDL as the hardware description language. The RTL model was verified by comparing its simulation results with those obtained from a behavioral model of the same turbo decoder written in C language.
dc.format.extent113 p.
dc.language.isoen
dc.publisherUniversity of Ottawa (Canada)
dc.subject.classificationEngineering, Electronics and Electrical.
dc.subject.classificationComputer Science.
dc.titleVHDL implementation of turbo codec
dc.typeThesis
dc.degree.nameM.A.Sc.
dc.degree.levelMasters
CollectionTh├Ęses, 1910 - 2010 // Theses, 1910 - 2010

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