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Showing results 1 to 6 of 6
Items
Date
Title
Contributor(s)
2011
Tunable Instruction Set Extension Identification
Shapiro, Daniel
;
Montcalm, Michael
;
Parri, Jonathan
;
Bolic, Miodrag
2011-02-24
Improved ISE Identification Under Hardware Constraint
Shapiro, Daniel
;
Bolic, Miodrag
2011-03-14
Soft Co-Processor Based Hardware Acceleration for Image Blending
Shapiro, Daniel
;
Parri, Jonathan
;
Desmarais, John-Marc
;
Kouri, Abdullah
;
Bergeron, Jean-Philippe
;
Bolic, Miodrag
2009
SING: A multiprocessor system-on-chip design and system generation tool
Branchaud, Marc
;
Shapiro, Daniel
;
Thareja, Vishal
;
Vijayakumar, Srivatsan
;
Bolic, Miodrag
2010-05-04T16:01:25Z
Static task scheduling for configurable multiprocessors
Groza, Voicu
;
Bolic, Miodrag
;
Montcalm, Michael
;
Shapiro, Daniel
2010-05-04T16:01:33Z
ITS: An ILP-based combined instruction/task static scheduling algorithm
Montcalm, Michael
;
Shapiro, Daniel
;
Groza, Voicu
;
Bolic, Miodrag
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Authors
6
Bolic, Miodrag
3
Montcalm, Michael
2
Groza, Voicu
2
Parri, Jonathan
1
Bergeron, Jean-Philippe
1
Branchaud, Marc
1
Desmarais, John-Marc
1
Kouri, Abdullah
1
Thareja, Vishal
1
Vijayakumar, Srivatsan
.
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Subjects
3
Instruction set extension
2
Multiprocessor
1
alpha blending
1
Application specific instruction-...
1
ASIP
1
configurable processor
1
FPGA
1
image processing
1
instruction enumeration
1
instruction selection
.
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Date
3
2011
2
2010
1
2009